1. Field of the Invention
The present invention relates in general to semiconductor integrated circuit device structures and associated methods of fabrication. More specifically, the present invention relates to a method for forming a local interconnect in an integrated circuit device.
2. Description of Related Art
Semiconductor integrated circuits (ICs) and associated fabrication methods are continuing and important areas of research and development. One significant area of focus for research and development investigation is the formation of local interconnect structures. Local interconnects are routing-restricted electrical interconnects that are typically used within a functional cell of an integrated circuit for various purposes such as electrically connecting a gate and drain of a transistor. Unlike other metal layers that are used for electrical coupling or contact, local interconnect structures are constructed without formation of an underlying insulating layer with etched contact openings that allows precise control of areas of electrical connection and electrical insulation. Thus local interconnect structures are not formed that extend across a region without electrically coupling to that region. For example, a local interconnect structure is not formed that extends across a gate region without electrically coupling to the gate region.
Throughout the history of semiconductor process technology, various methods for forming local interconnect structures have been developed. In some conventional integrated circuit fabrication methods, heavily-doped polysilicon is used as a local interconnect material. In other integrated circuit fabrication techniques, a polysilicon layer having a metal silicide layer is a suitable interconnect material. One disadvantage of a metal silicide interconnect layer is that the polysilicon layers are typically N-type doped layers that are unsuitable for forming electrical contacts to source/drain (S/D) regions of PMOS devices. More recently, other local interconnect methods have been devised including selective formation of TiSi.sub.2, Ti:W over CoSi.sub.2 and TiN over TiSi.sub.2. While each interconnect formation scheme has advantages over the usage of a polysilicon layer, each scheme also has process limitations that restrict wide-spread usage.
For example, a selective TiSi.sub.2 formation method employs a reaction of titanium (Ti) metal with silicon (Si) to form a silicide. A titanium (Ti) layer is deposited. Then an amorphous silicon (Si) layer or film is formed. The silicon film is patterned and the sample is heated so that silicide (TiSi.sub.2) is formed in regions of amorphous silicon after patterning of the silicon. (The silicide (TiSi.sub.2) formation is selective to the patterned Si layer.) Any unreacted titanium is removed in a final etch. The silicide formation process has several disadvantages. First, etching the amorphous silicon overlying the titanium layer utilizes an etch process that has a high selectivity of silicon over titanium. An etch process with high selectivity to silicon over titanium is difficult to attain. The selectivity problem of the process creates a second problem, a difficulty in removing excess silicon from gate edges. Local interconnects are not easily formed using the silicide formation process and etch difficulties results in unintended electrical contacts to undesired areas, thereby reducing reliability of the integrated circuit.
Another conventional technique for forming local interconnects is described by S. Wolfe in Silicon Processing for the VLSI Era, Volume 2, (1990), pp. 166-67. A layer of titanium is deposited followed by a first anneal to form a TiN layer. TiSi.sub.2 regions are formed essentially simultaneously. In a subsequent step, the TiN is patterned and etched to form intended local interconnect structures. A second anneal reduces sheet resistivities of the TiN layer and TiSi.sub.2 regions to desired levels. One disadvantage of the local interconnect formation method is difficulty in controlling TiSi.sub.2 formation. Typically, a titanium layer is deposited so that silicide (TiSi.sub.2) formation consumes the entire titanium layer. Therefore the amount of silicide that is formed and the amount of silicon that is consumed are controlled by the thickness of the titanium layer. Since the local interconnect formation technique includes formation of both silicide (TiSi.sub.2) and titanium nitride (TiN) so that only a portion of the titanium layer thickness for forming the silicide while, some control method is necessary to ensure that some Ti remains for TiN formation. Therefore, unlike a typical TiSi.sub.2 process, both time and temperature are controlled to regulate silicon consumption. Unfortunately, by controlling time and temperature for silicon consumption regulation creates undesirable variability in junction depths for doped areas.
Another difficulty is that the titanium nitride layer should have a uniform thickness to form suitable local interconnect structures. The formation of a uniform thickness titanium nitride layer is difficult to achieve since the rate of titanium nitride formation varies depending on the composition of materials in contact with the precursor titanium layer and depending upon whether the lower portion of the titanium layer is used to form silicide. In summary, the local interconnect formation method has several difficulties that result in unsuitable variations in resistivity and local interconnect viability.
What is needed is a technique for forming local interconnect structures that is simpler, easier to perform, lower cost, and results in more reliable local interconnect structures with lower and more consistent resistance and resistivity. What is needed is a local interconnect fabrication method that results in a more reliable local interconnect structure. What is further needed is a method for forming reliable and low resistivity local interconnect structures that is easy to perform and integrates easily into an existing integrated circuit fabrication process.